Voltage regulation is commonly required to prevent variation in the supply voltage powering various microelectronic components, such as digital ICs, semiconductor memories, display modules, hard disk drives, RF circuitry, microprocessors, digital signal processors and analog ICs, especially in battery-powered applications such as cell phones, notebook computers and consumer products.
Since the battery or DC input voltage of a product often must be stepped-up to a higher DC voltage, or stepped-down to a lower DC voltage, such regulators are referred to as DC-to-DC converters. Step-down converters, commonly referred to as Buck converters, are used whenever a battery's voltage is greater than the desired load voltage. Step-down converters may comprise inductive switching regulators, capacitive charge pumps, and linear regulators. Conversely, step-up converters, commonly referred to boost converters, are needed whenever a battery's voltage is lower than the voltage needed to power its load. Step-up converters may comprise inductive switching regulators or capacitive charge pumps.
Of the aforementioned voltage regulators, the inductive switching converter can achieve superior performance over the widest range of currents, input voltages and output voltages. The operation of a DC/DC inductive switching converter is based on the simple principle that the current in an inductor (coil or transformer) cannot be changed instantly, and that an inductor will produce an opposing voltage to resist any change in its current.
The basic principle of an inductor-based DC/DC switching converter is to switch or “chop” a DC supply voltage into pulses or bursts, and to filter those bursts using a low-pass filter comprising an inductor and a capacitor to produce a well-behaved time-varying voltage, i.e. to change a DC voltage into an AC voltage. By using one or more transistors switching at a high frequency to repeatedly magnetize and de-magnetize an inductor, the inductor can be used to step-up or step-down the converter's input voltage, producing an output voltage different from its input voltage. After changing the AC voltage up or down using magnetics, the output voltage is then rectified back into a DC voltage, and filtered to remove any ripples.
The DC/DC converter is typically implemented using MOSFETs with a low on-state resistance, commonly referred to as “power MOSFETs”. Using feedback from the converter's output voltage to control the switching conditions, a constant well-regulated output voltage can be maintained despite rapid changes in the converter's input voltage or its output current.
To remove any AC noise or ripple generated by the switching action of the MOSFETs, an output capacitor is placed across the output terminal of the switching regulator circuit. Together the inductor and the output capacitor form a “low-pass” filter able to prevent most of the MOSFETs' switching noise before it reaches the load. The switching frequency, typically 1 MHz or more, must be “high” relative to the resonant frequency of the filter's “LC” tank. Averaged across multiple switching cycles, the switched inductor behaves like a programmable current source with a slow-changing average current.
Since the average inductor current is controlled by MOSFETs that are either biased as “on” or “off” switches, the power dissipation in the MOSFETs is theoretically small, and high converter efficiencies, in the 80% to 90% range, can be realized. Specifically when a power MOSFET is biased as an on-state switch using a “high” gate bias, it exhibits a linear I-V drain characteristic with a low RDS(on) resistance typically 200 milliohms or less. At 0.5 A for example, such a device will exhibit a maximum voltage drop ID·RDS(on) of only 100 mV despite its high drain current. Its power dissipation during its on-state conduction time is ID2·RDS(on). In the example given, the power dissipated while the transistor is conducting is (0.5 A)2·(0.2Ω)=50 mW.
Thus a power MOSFET has its gate biased to its source, i.e. so that VGS=0. Even with an applied drain voltage VDS equal to a converter's battery input voltage Vbatt, a power MOSFET's drain current IDSS is very small, generally well below one microampere and more generally in the range of nanoamperes. The current IDSS primarily comprises junction leakage.
For these reasons, a power MOSFET used as a switch in a DC/DC converter is efficient, since in its off-condition it exhibits low currents at high voltages, and in its on-state it exhibits high currents at a low voltage drop. Excepting switching transients, the ID·VDS product in the power MOSFET remains small, and power dissipation in the switch remains low.
A critical component in switching regulation is the rectifier function needed to convert, or “rectify”, the synthesized AC output of the chopper back into a DC voltage. To ensure that the load never sees a reversal of polarity in voltage, a rectifier diode is placed in the series path of the switched inductor and the load, thereby blocking large AC signals from the load. The rectifier may be located topologically either in the high-side path, i.e., between the positive terminal of the power or battery input and the positive terminal of the output, or on the low-side path, i.e. in the “ground” return path. Another function of the rectifier is to control the direction of energy flow so that current only flows from the converter to the load and does not reverse direction.
In one class of switching regulators, the rectifier function employs a P-N junction diode or a Schottky diode. The Schottky diode is preferred over the P-N junction because it exhibits a lower forward voltage drop than P-N junctions, typically 400 mV instead of 700 mV, and therefore dissipates less power. During forward conduction, a P-N diode stores charge in the form of minority carriers. These minority carriers must be removed, i.e. extracted, or recombine naturally before the diode is able to block current in its reverse-biased polarity.
Because a Schottky diode contains a metal-semiconductor interface rather than a P-N junction, ideally it does not utilize minority carriers to conduct and therefore stores less charge than a P-N junction diode. With less stored charge, the Schottky diode is able to respond more quickly to changes in the polarity of the voltage across its terminals and to operate at higher frequencies. Unfortunately Schottky diodes have several major disadvantages, one of which is that it exhibits significant and unwanted off-state leakage current, especially at high temperatures. As a result, there is unfortunately a fundamental tradeoff between a Schottky diode's relatively high off-state leakage current and its relatively low forward-biased voltage drop.
Moreover, the lower its voltage drop during conduction, the leakier it becomes in its off state. The leakage current also exhibits a positive voltage coefficient of current, so that as the leakage current increases, power dissipation also increases, causing the Schottky diode to leak more and dissipate more power, causing even more heating. With such positive feedback, localized heating can cause a hot spot to get hotter and “hog” more of the leakage until the spot reaches such a high current density that the device fails, a process known as thermal runaway.
Another disadvantage of a Schottky diode is the difficulty of integrating it into an IC using conventional wafer fabrication processes and manufacturing. Metals with the best properties for Schottky diodes are not commonly available in IC processes. Some commonly available metals exhibit too high a voltage barrier, i.e. too high a voltage drop, while other commonly available metals exhibit too low a barrier potential, i.e. they allow too much leakage current.
Despite these limitations, many switching regulators today use P-N diodes or Schottky diodes for rectification. As a two-terminal device, a rectifier does not require a gate signal to control when it conducts. Aside from current resulting from the transient charge storage, the rectifier naturally prevents reverse currents, so that energy cannot flow from the output capacitor and electrical load back into the converter and its inductor.
To reduce voltage drops and conduction losses, power MOSFETs are sometimes used in place of Schottky rectifier diodes in switching regulators. Operation of a MOSFET as a rectifier is often accomplished by placing the MOSFET in parallel with a Schottky diode and turning on the MOSFET whenever the diode conducts, i.e. synchronous to the diode's conduction. In such an application, the MOSFET is sometimes referred to as a “synchronous rectifier.”
Since a synchronous rectifier MOSFET can be sized to have a low on-resistance and a lower voltage drop than a Schottky diode, when the Schottky diode is conducting current is diverted from the diode to the MOSFET channel, and the overall power dissipation in the “rectifier” is reduced. Most power MOSFETs includes a parasitic source-to-drain diode. In a switching regulator, the orientation of this intrinsic P-N diode must be the same polarity as the Schottky diode, i.e. cathode to cathode, anode to anode. Since the parallel combination of the silicon P-N diode and Schottky diode carries current only for brief intervals, known as “break-before-make” intervals, before the synchronous rectifier MOSFET turns on, the average power dissipation in the diodes is low, and the Schottky diode is often eliminated altogether.
Assuming that the transistor switching events are relatively fast compared to the oscillating period of the regulator, the power losses during switching can be considered negligible or alternatively treated as a fixed power loss. Overall, the power lost in a low-voltage switching regulator can be estimated by considering the conduction and gate drive losses. At multi-megahertz switching frequencies, however, the switching waveform analysis becomes more significant and the MOSFET's drain voltage, drain current, and gate voltage must be analyzed as a function of time.
A synchronous rectifier MOSFET, however, unlike a Schottky or P-N junction diode, allows current to flow bi-directionally and must be operated with precise timing on its gate signal to prevent a reverse current flow, an unwanted type of conduction that lowers efficiency, increases power dissipation and heating, and may damage the device. By slowing down the switching rates and increasing the turn-on delays, efficiency can often be traded for improved robustness in DC/DC switching regulators.
Applying the above principles, present inductor-based DC/DC switching regulators are implemented in a wide range of circuits, inductors, and converter topologies. Broadly, they can be divided into two major topologies, non-isolated and isolated converters.
The most common isolated converters include the flyback converter and the forward converter, and require a transformer or coupled inductor. At higher power, full-bridge converters are also used. Isolated converters are able to step up or step down the input voltages depending on the primary to secondary winding ratio of the transformer. Transformers with multiple windings can produce multiple outputs simultaneously, including voltages both higher and lower than the input. The disadvantage of transformers is they are large compared to single-winding inductors and suffer from unwanted stray inductances.
Non-isolated converters include step-down. Buck converters, step-up boost converters, and Buck-boost converters. Buck and boost converters are efficient and compact in size, particularly when operating in the megahertz frequency range, where inductors of 2.2 μH or less may be used. Such topologies produce a single regulated output voltage per coil, and require a dedicated control loop and a separate PWM controller for each output to constantly adjust the on-times of the MOSFET switches so as to regulate the output voltage.
In portable and battery powered applications, synchronous rectification is commonly employed to improve efficiency. A step-up boost converter employing synchronous rectification is known as a synchronous boost converter. A step-down Buck converter employing synchronous rectification is known as a synchronous Buck regulator.
Non-Synchronous Versus Synchronous Buck Converter Operation
As illustrated in FIG. 1A, a prior art Buck converter 1 includes a P-channel or N-channel power MOSFET 2, an inductor 3, an output capacitor 4, a Schottky rectifier diode 5, and a pulse-width modulation (PWM) controller 6. Inductor 3, MOSFET 2 and rectifier 5 share a common node referred to here as the “Vx” node (sometimes referred to as the “Lx” node), which exhibits a voltage Vx. A diode 7 is parasitic to MOSFET 2 and remains reverse-biased and off throughout regular operation of Buck converter 1.
Through the switching action of power MOSFET 2, the Vx node switches “rail-to-rail,” exhibiting a potential alternating between approximately Vbatt when MOSFET 2 is on (and conducting a current IL(on)) to slightly below ground when MOSFET 2 is off (when a current IL(off) recirculates through rectifier diode 5). The waveform of Vx is illustrated in graph 10 of FIG. 1B, where Vx when MOSFET 2 is conducting (curve 11) is given by the expression (Vbatt−I·RDS(on)) and Vx when MOSFET 2 is off (curve 14) is given by −Vf.
At time t=12, after a duration ton, inductor 3 drives voltage Vx negative, and depending on the design and layout of converter 1 at this point Vx may experience some voltage overshoot and unwanted oscillations or ringing 13. After an interval toff, at time 15, MOSFET 2 turns on, and after diode 5 recovers from any stored charge, Vx exhibits a positive transition 15 and the entire cycle repeats.
In a synchronous Buck converter, rectifier diode 5 is replaced by a second power MOSFET. As shown in FIG. 2A, a synchronous Buck converter 20 includes a high-side power MOSFET switch 22, an inductor 23, an output capacitor 24, and a low-side synchronous rectifier MOSFET 21 with anintrinsic parallel diode 25. The gates of MOSFETs 22 and 21 are driven by break-before-make (BBM) circuitry 27 and controlled by a PWM controller 26 in response to a feedback voltage VFB from the converter's output present across output capacitor 24. BBM operation is needed to prevent a short between Vbatt and ground through MOSFETs 21 and 22.
The waveform for Vx in synchronous regulator 20 is illustrated in graph 30 of FIG. 2B, where through the switching action of high-side power MOSFET 22, the Vx node switches rail-to-rail, exhibiting a potential alternating between approximately Vbatt when said MOSFET is on (and conducting current IL(on)) and to slightly below ground when MOSFET 22 is off (when a current IL(off) recirculates through MOSFET 21). Vx is illustrated in graph 30 as being equal to Vbatt−I·RDS1(on) when MOSFET 22 is conducting (curve 31).
At time t=32, after a duration ton, inductor 23 drives Vx negative, and depending on the design and layout of converter 20 may experience some voltage overshoot and unwanted oscillations or ringing 33 before settling to a voltage −Vf. At time t=34 after a break-before-make time interval tBBM (as determined by BBM circuitry 27), Vx is reduced by conducting synchronous rectifier MOSFET 21 to a magnitude (−I·RDS2(on)), reducing the power loss compared to dissipation in P-N diode 25.
At a time t=35, just before high-side MOSFET 22 is turned on, synchronous rectifier MOSFET 21 is shut off and Vx returns to −Vf, (curve 36), the forward voltage drop across diode 25. After an interval toff, MOSFET 22 turns on, and after P-N diode 25 recovers from any charge storage, Vx exhibits a positive transition 37. Depending on the recovery of P-N diode 25 Vx may exhibit an over-voltage spike 38. Following spike 38 and subsequent ringing Vx stabilizes at (Vbatt−I·RDS1(on)) and the entire cycle repeats.
High-side MOSFET 22 may be an N-channel or P-channel MOSFET. The grounded synchronous rectifier MOSFET 21 is more conveniently implemented as an N-channel MOSFET. Diode 28, which remains off and reverse-biased during the normal operation of converter 22, is a P-N diode intrinsic to high-side MOSFET 22. Since diode 28 does not conduct under normal operation, it is shown with dotted lines. Diode 25, intrinsic to synchronous rectifier MOSFET 21, becomes forward-biased whenever high-side MOSFET 22 is off but carries a substantial current only when MOSFET 21 is off. A Schottky diode may be included in parallel with MOSFET 21 but with series inductance may not operate fast enough to divert current from the forward-biased diode 25.
If the percentage of the time that energy flows from the battery or power source into the DC/DC converter (i.e. the percentage of time when high-side MOSFET switch 22 is on and inductor 23 is being magnetized) is defined as the duty factor D of the converter, the output-to-input voltage ratio of the converter is proportionate to the duty factor, i.e.
            V      out              V              i        ⁢                                  ⁢        n              =      D    ≡                  t        on            T      
While this equation describes a wide range of conversion ratios, a Buck converter cannot smoothly approach a voltage ratio of zero or unity without requiring extremely fast devices and circuit response times. Considering these factors, the duty factor of a Buck converter is limited in practice to the range of 5% to 95%.
Forced Diode Recovery Operation and Impact
Diode recovery is a major source of power loss and electrical noise in switching regulators. In graph 30 of FIG. 2B, the high dV/dt voltage transient 37 and voltage overshoot 38 occur because of stored charge in diode 25. This phenomenon is better explained in graph 40 of FIG. 2C, wherein the rectifier current Irect and the voltage Vx are plotted against time. Prior to time t1, as shown in inset 41, high-side MOSFET 22 is off and the low-side synchronous rectifier MOSFET 21 is on, carrying a current Irect that is the same as the current IL flowing through inductor 23, i.e. Irect=IL (curve 50). During this interval Vx (the voltage across synchronous rectifier MOSFET 21) is equal to Irect·RDS2(on) (curve 60).
At time t1 MOSFET 21 turns off and P-N junction diode 25 must carry the inductor current IL by itself. As a result, Vx increases in absolute magnitude to −Vf (curve 61). During this break-before-make interval, charge is stored in P-N junction diode 25. This condition, illustrated in inset 42, persists until time t2, when high-side MOSFET 22 once again turns on.
As shown in inset 43, the instant MOSFET 22 turns on it is biased with a large drain voltage and a small gate voltage operating in its saturated region as a controlled current source, ramping up in current. As the current in MOSFET 22 ramps up, it supplies an increasing percentage of current in inductor 23, diminishing the current burden in rectifier diode 25 as evidenced by the linear drop in Irect current (curve 51). During this ramp-up, the absolute value of the voltage across reverse-biased diode 25 declines gradually by an amount ΔVx (curve 62), but diode 25 remains reverse-biased and Vx is still below ground.
If no charge were present in P-N diode 25, at time t2 when current Irect reaches zero, diode 25 would turn off and Irect would never go negative. But because of stored charge in P-N diode 25, the current ramp (curve 51) in diode 25 reverses polarity and actually goes negative, with current flowing into the cathode of diode 25. As the charge in the diode depletes and recombines, the voltage across diode 25 approaches zero (curve 63).
At time t6 the voltage across rectifier diode 25 reverses polarity and the diode reverse recovery current reaches its peak (point 52). Vx then rises rapidly with a high dV/dt slew rate (curve 64), powered by a high side MOSFET 22 which is now biased into a full-on condition with an on-state resistance RDS1(on) as represented schematically in inset 44. During this interval, high-side MOSFET 22 must supply both the current through inductor 23 and the reverse-recovery current in diode 25. A reverse current in diode 25 means current is flowing into the cathode of the P-N junction diode even though the diode is reverse-biased and theoretically should be off. By temporarily conducting a negative current while being reverse-biased (curve 53), diode 25 produces an energy loss Err during the interval Δtrr=t9−t6 and given by
      E    rr    ≈            ∫              t        6                    t        9              ⁢                            I          ⁡                      (            t            )                          ·                  V          ⁡                      (            t            )                              ⁢              ⅆ        t            
Err can be substantial. Reverse currents of 1 A or more may occur with instantaneous power (Irr(peak)·Vbatt) losses of over 4W. Since this reverse current is supplied through Vbatt-connected high-side MOSFET 22, the energy loss is similar to shoot-through current losses, and using a triangular approximation contributes an average power loss of (2W)·Δtrr/T.
Moreover, because of the high dV/dt in the region of curve 63, Vx over-shoots the battery input voltage Vbatt. The cause for this overshoot is represented schematically in equivalent circuit 100 of FIG. 2D, where the battery is represented by voltage source 101, the inductor by current source 103, the charged output capacitor by voltage source 104, the high side MOSFET with drain current I1 represented by controlled current source 102, and the recovery diode 105 by a junction capacitance 107 and a minority carrier diffusion capacitance by P-N junction diode 106.
Inset 108 traces the change in I1 with the drain voltage VDS1 of high-side MOSFET 102 over time, where VDS1=(Vbatt−Vx). For example, at time t2 the high-side MOSFET is off and current I1 is zero. As the gate voltage of the high-side MOSFET operating in its saturated region increases (bracket 109) in magnitude from VG(t3) to VG(t7), the magnitude of current I1 increases without significant changes in drain voltage VDS1. For example, at time t6, Vx=0 and the drain voltage has a voltage VDS1=Vbatt (point 112). The voltage during this time period is nearly constant because diode 105 still contains stored charge and will not let Vx change. Beyond time t7, however, the diode “let's go” and the voltage changes rapidly (curve 111).
Referring again to FIG. 2C, at time t8 the voltage overshoot may reach a peak voltage Vpeak (point 65). If the magnitude of Vpeak is 600 mV or more greater than Vbatt, it will momentarily forward-bias the high-side diode 28, storing charge and causing noise and further oscillations (curve 66).
Finally, at time t9, as shown in inset 67 in FIG. 2C, the Vx voltage stabilizes at Vbatt (curve 67), the rectifier current Irect is zero (curve 54), and the reverse recovery of diode 25 is complete. Referring again to inset 108 of FIG. 2D, at point 113 the gate of high-side MOSFET 102 reaches a bias VG(t8) and MOSFET 102 enters its linear region (curve 110), no longer behaving as a controlled current source. In the linear region 110, the drain current I1 and drain voltage VDS1 do not change substantially.
In conclusion, diode recovery occurs in a synchronous Buck converter as a consequence of break-before-make operation, where both high-side and low-side MOSFETs are momentarily off. The charge stored in the diode leads to current spikes between the battery input and ground, i.e. across the converter's power input. It also causes increased power dissipation, loss of efficiency, high dV/dt slew rates, voltage overshoot, noise, and unwanted ringing and oscillations. Such oscillations may also limit the maximum operating frequency of the switching regulator.
Gate Drive Losses
Another source of power loss in a Buck converter results from the charging and discharging of the MOSFET gate capacitances. The origin of gate drive loss is represented schematically in the Buck converter 120 of FIG. 3A, where a P-channel MOSFET 122 includes a drain-to-gate capacitance CDG (capacitor 126), gate-to-source capacitance CGS (capacitor 128), and drain-to-source capacitance CDS (capacitor 127). To turn MOSFET 122 on and off, gate driver 125 must supply transient gate drive currents iG(t) to charge and discharge the gate connected CDG and CGS capacitors 126 and 128 at the desired frequency. All of the MOSFET's capacitors shown are voltage variable.
The magnitude of drain-to-gate capacitor 126 is especially important since it appears larger in actual operation than its small signal equivalent value. This amplifying effect on input capacitance, originally known as the “Miller” effect in bipolar amplifiers, is a consequence of voltage gain in converter 120. This voltage gain Av(t) occurs during operating conditions when MOSFET 122 is saturated and behaves like a programmable current source. The CDG input capacitance is scaled in proportion to this gain, which varies during a switching transient.
Even though the parasitic capacitance in MOSFET 122 gives rise to gate drive and switching losses, the power required to drive the MOSFET's capacitance is manifested in gate driver 125, not in the MOSFET itself and must be supplied by the battery input source Vbatt. Changing the high-side MOSFET from a common-source configured P-channel device to a source-follower N-channel device does not eliminate the Miller feedback effect.
In Buck converter 140 of FIG. 3B, for example, a high-side N-channel MOSFET 142 includes a drain-to-gate capacitance CDG (capacitor 146), a gate-to-source capacitance CGS (capacitor 148), and a drain-to-source capacitance CDS (capacitor 147). To turn MOSFET 142 on and off, a source-referenced gate driver 145 must supply transient gate drive currents iG(t) to charge and discharge the gate connected CDG and CGS (capacitors 146 and 148) at the desired frequency. All of the MOSFET's capacitors shown are voltage variable.
Even though the drain of N-channel MOSFET 142 is biased at a fixed potential Vbatt, gate driver 145 must float with the voltage Vx, so that the gate potential VG changes with respect to the drain potential VD during a switching transient. As a consequence the magnitude of input capacitance is still amplified by the Miller effect and must be driven by gate driver 145. The power needed to drive the extra capacitance is delivered from bootstrap capacitor 149, which is ultimately is supplied from Vbatt through forward-biased bootstrap diode 150 whenever Vx is at ground.
Gate drive loss therefore occurs driving the high-side MOSFET in a Buck converter regardless of whether the device is an N-channel source-follower device or a P-channel common-source configured device. Rather than calculate the power loss in a voltage variable capacitor, a more accurate measurement of gate drive requirements of a power MOSFET is the gate charge curve 160 shown in FIG. 3C. The graph illustrates a plot of the gate-to-source voltage VGS of the MOSFET versus the total gate charge QG needed to drive the gate to that voltage. Taking into account changing bias conditions, the aforementioned Miller effect, and non-linear capacitances, the gate charge measurement method is more useful than capacitance calculations in determining gate drive loss.
The gate charge curve is generated using a power MOSFET with its gate driven by a constant current source IG. To properly model the effect of gate to drain feedback, the MOSFET drives a load comprising a resistor or current-source powered from Vbatt. The device is characterized by starting with an off MOSFET and zero gate bias (point 161) and at a start time, but switching on the current source driving the MOSFET's gate. As the gate VGS voltage rises to its threshold and beyond, then at VGS(on) the transistor has adequate transconductance to carry the load current and the drain voltage begins to drop (curve 163).
During the dVDS/dt transition, the gate-to-drain capacitance CDG must be charged by equal and opposite charges coming from the drain and gate terminals. Since the constant gate current is charging CGD no charge is left over to charge the gate-to-source capacitor CGS, and as a result the gate potential becomes constant (curve 164). This plateau in gate voltage represents the charge needed to satisfy charge neutrality and quantitatively measures drain-to-gate feedback, i.e. the Miller effect over the entire transient. Once the drain voltage drops to semi-constant value, the MOSFET enters its linear region where VDS=ID·RDS1 and the gate voltage VGS resumes its upward transition.
Since the gate current in the measurement is a constant magnitude IG, the abscissa of graph 160 can be changed from time “t” to gate-charge QG by the linear relationship QG=IG·t. As shown in graph 160, the drain voltage VDS(t) and gate voltage VGS(t) can then be plotted against gate charge. As illustrated there is a unique and specific amount of gate charge QG needed to drive the gate to a specific gate voltage 162 and drain voltage 165. Since charge is conserved, the shape of the graph doesn't depend on the speed by which the measurement was made. If the IG is increased, the time t is decreased by in proportion and graph 160 remains unchanged.
The effective input capacitance of the power MOSFET switching between “off” with gate voltage VGSα=0 and “fully-on” with the gate at potential VGSβ is given by
      C    eq    =                    Δ        ⁢                                  ⁢        Q                    Δ        ⁢                                  ⁢        V              =                  Q                  G          ⁢                                          ⁢          β                            V                  GS          ⁢                                          ⁢          β                    where QGβ is the sum of all the charges required for the MOSFET to transition from off to on, i.e. QG(on), then through its saturation region ΔQDG and into its linear region by an amount ΔQD(lin), or as
      C    eq    =                    Q                  G          ⁢                                          ⁢          β                            V                  GS          ⁢                                          ⁢          β                      =                                        Q            G                    ⁡                      (            on            )                          +                  Δ          ⁢                                          ⁢                      Q            DG                          +                  Δ          ⁢                                          ⁢                                    Q              G                        ⁡                          (              lin              )                                                  V                  GS          ⁢                                          ⁢          β                    
Since charge is conserved, the equivalent capacitance Ceq to drive the MOSFET's gate to a voltage VGSβ is path independent, meaning that the power needed to bias the device to a fully on condition is independent of the drive technique. Gate-drive power loss is however dependent on the drain bias Vbatt, which determines the width of the plateau ΔQDG. The higher the Vbatt voltage is, the larger the magnitude of VDS and the wider the gate plateau ΔQDG.
In essence, ΔQDG plateau (curve 164) in graph 160 represents the small-signal Miller feedback effect on input capacitance as measured in a large scale MOSFET switching transient, and accurately accounts for the total energy lost in the transient. Even if a voltage source is used to power the gate during switching, the energy and power losses remain the same. Only by minimizing the drain voltage transition causing the ΔQDG can the losses be reduced in any given power MOSFET. Unfortunately since Vbatt is the input to a DC/DC converter, it is not available as a variable to control gate drive losses.
Actual power loss depends on the relative relationship of the interval of switching losses with respect to the overall period. The primary losses, however, comprise I2·RDS conduction losses and QG·VG gate drive losses as given byPloss≈Pconduction+Pgate-drive=I2RDS1D+QG·VG·f 
In a DC/DC converter, the duty factor D is controlled by feedback to maintain a fixed output-to-input conversion ratio. For a fixed voltage input voltage, output voltage and load current, only frequency determines the weighting of these two loss components. At low frequencies gate drive losses dominate. At high frequencies switching losses dominate.
Worse yet, MOSFET device operation requires an unavoidable tradeoff between these losses. This intrinsic tradeoff can best be understood by converting graph 160 into graph 170 by swapping the ordinate and abscissa axes as shown in FIG. 3D. As shown, the QG gate charge curve includes off portion 161, saturation portion 164, and linear region 162 just as in graph 160 where QG increases proportionally with increasing VGS. On the same graph 170, RDS on-resistance curve exhibits a hyperbolic dependence on gate drive, declining with increasing bias. At the edge of saturation, the on-resistance RDS declines rapidly (curve 171) into linear operation (curve 172) and reaches a minimum value (curve 173) at approximately a gate bias of VGSβ.
The tradeoff of on-resistance and gate-charge is illustrated by their product QG·RDS, shown by the dashed curve in graph 160. Since both terms contribute to loss, minimizing the QG·RDS product represents the maximum converter efficiency and minimum power loss. In region 174, the QG·RDS product declines because on-resistance 171 is dropping. In region 176 the QG·RDS product increases because QG is increasing. In between an optimum bias condition 175 exists where the QG·RDS product is minimized. In a real converter, the VGS cannot be maintained at this optimum condition since VGS varies with the battery input voltage. In essence, the QG·RDS product is a figure-of-merit for a given technology and device design.
Without redesigning the device and process, the only means to reduce the gate drive loss in its operation is to limit the maximum VDS during device operation. Unfortunately, the Buck and synchronous Buck converters impose the full battery input voltage Vbatt across the high-side MOSFET during switching, maximizing ΔQDG and the associated gate drive losses.
In contrast, the synchronous rectifier MOSFET does not change between conducting and non-conducting states with any significant drain bias, so its gate drives losses are not aggravated by the Miller effect and an excessive ΔQDG plateau.
Problems with Buck Converters
As shown above, a Buck converter exhibits poor efficiencies and excessive heating because of power dissipation in its rectifier. Schottky diodes suffer from excessive leakage and the risk of thermal runaway. Synchronous rectification eliminates the rectifier conduction losses and heating problems in conventional non-synchronous Buck converters, but cannot eliminate all the problems of a Buck converter.
Break-before-make operation, for example, needed to prevent shoot-through conduction in the high-side and low-side power MOSFETs, requires a dead time when both devices are momentarily off. During that interval, a P-N diode parallel to the synchronous rectifier MOSFET must carry the full inductor current and in so doing store charge. This stored charge leads to forced diode recovery causing a current path across the converter's input, and causes high dV/dt slew rates, voltage over-shoot, oscillations and noise—the same as in a non-synchronous Buck converter.
Moreover, eliminating the diode is not an option. Circuit 200 of FIG. 4A illustrates a Buck converter with the rectifier diode removed, comprising a high-side MOSFET 202 with an intrinsic parallel diode 205, an inductor 203 and an output capacitor 204. Unlike in a Buck or synchronous Buck converter, no diode is present between the node Vx and ground. The resulting switching waveforms of operating circuit 200 are shown in graph 210 of FIG. 4B where once MOSFET 202 is turned on, the drain and inductor currents ramp linearly 211 while the voltage across MOSFET 202 is only IL(t)·RDS(on), meaning Vx≈Vbatt, as shown by curve 215.
At a time t1, when MOSFET 202 is turned off, VX immediately exhibits a negative going voltage transient (curve 216) in order to maintain a constant inductor current (point 212). With no rectifier, the voltage at node Vx goes negative, below ground, without limitation until the VDS1 across off-state MOSFET 202 exceeds the avalanche breakdown BVDSS1 of diode 205, driving it into breakdown. The negative Vx voltage overshoots and rings slightly (curve 217) until it settles at a voltage Vx=(Vbatt−BVDSS1). If MOSFET 202 is fragile, i.e. not robust, it will immediately exhibit snapback I-V characteristics and destroy itself. If MOSFET 202 is robust, it will sustain the breakdown voltage BVDSS1 until the current ramps down to zero (curve 213) at time t2, when MOSFET 202 ceases conduction At that time, inductor 203 behaves like a wire, not a current source and Vx jumps up from point 218 to the capacitor voltage Vout as shown by curve 219.
Such a device is referred to as a rugged power MOSFET. Rugged MOSFETs are rated by the magnitude of energy Ej they can absorb before the silicon semiconductor or conductor materials in the MOSFET melt from overheating. A thermal failure is not considered a failure of ruggedness. Power device operation in this manner is known as unclamped inductive switching, or UIS, and is common in many solenoid and motor drives used in automotive applications. Because energy is dumped from inductor 203 into diode 205, UIS operation has very poor energy efficiency. So removing the rectifier diode from Buck converter is not a viable option.
Unfortunately leaving the rectifier diode in also creates problems, especially under light load conditions where it causes the inductor current to become intermittent. This phenomenon is illustrated in graph 225 of FIG. 5A. For a Buck converter operating at a high currents IL(high) the inductor current alternates in successive upward and downward ramps reaching a maximum current (point 227) and a minimum (point 226) both well above zero. At lower inductor currents IL(mid) the peak current (point 229) is well above zero but the minimum value (point 228) approaches zero.
Any inductor current IL below this minimum value causes the inductor current to become discontinuous. In such cases the inductor current has a positive peak current (point 231) but has a minimum value truncated to zero at points 230 and 232, the diode conduction time now being limited to a small percentage of the total period T and essentially conducting at a different frequency and duty factor than the off-time of MOSFET 236. Discontinuous conduction increases ripple and noise in the converter's output.
In a synchronous Buck converter operating in light load such as circuit 235 of FIG. 5B, care must also be taken to turn off low-side MOSFET 237 before the current reaches zero and IL reverses polarity. If the synchronous rectifier MOSFET remains on too long, the inductor current will reverse direction as shown by curve 233. A current reversal means current in inductor 239 will flow backwards from the load 242 and into the regulator, moving energy in the wrong direction away from load 241 and output capacitor 240 and into converter circuitry, during which efficiency suffers.
Circuit 235 will therefore oscillate with current IL(forward) flowing in part of the cycle and IL(reverse) flowing for the rest. Some electrical loads 241 do not operate properly under AC conditions. But sensing and shutting of synchronous rectifier MOSFET 237 is problematic because of noise on Vx and because there is no easy way to accurately measure low magnitude currents in inductor 239. If MOSFET 237 is shut off too late, the inductor current reverses and energy is lost. If it is shut off prematurely, diode 238 has to carry current for a longer time and stores more charge. It also exhibits oscillations at the time the synchronous rectifier is shut off, lowering efficiency and generating noise.
Moreover, at very light loads the high side MOSFET's on-time becomes so short the entire converter is forced to operate at a variable frequency with almost no inductor current flowing, i.e. nearly off. Being nearly off makes it difficult to react to sudden changes in the load current and can lead to poor transient regulation, especially in light load operation.